June 26, 2020

The team of Sakai/Irie Laboratory and Shioya Laboratory
won 3rd place in the 1st Instruction Prefetching Championship

Tomoki Nakamura (D1), Toru Koizumi (D1), Yuya Degawa (M2), Hidetsugu Irie (Associate Prof.), Shuichi Sakai (Prof.), and Ryota Shioya (Associate Prof.) won 3rd place in the 1st Instruction Prefetching Championship held on May 31st, 2020.

The Championship was held in conjunction with the Int. Symp. on Computer Architecture, which is a major international event for computer architects. In this contest, each team designs an instruction cache prefetcher within a given regulation and competes for CPU performance, which targets the cutting-edge improvement of instruction cache prefetching technology, which has a large impact on CPU performance.
The contest was heated with participants from around the world, including the world's leading experts in this field, from universities and research institutions. Among these, the "D-JOLT" prefetcher, which is powered by the original technology of the team, showed excellent performance and won third place.
(Awards were given to the first through third place winners.)

The 1st Instruction Prefetching Championship
D-JOLT: Distant Jolt Prefetcher
Tomoki Nakamura (The University of Tokyo), Toru Koizumi (The University of Tokyo), Yuya Degawa (The University of Tokyo), Hidetsugu Irie (The University of Tokyo), Shuichi Sakai (The University of Tokyo), Ryota Shioya (The University of Tokyo)

Sakai/Irie Lab (Information & Communication Engineering)
Shioya Lab (Creative Informatics)