Professor Guri Sohi 講演会のお知らせ

　梅雨の候ですが、皆様お変わりなくお過ごしのことと存じます。

　ウイスコンシン大学Guri Sohi教授による講演会を下記のように開催いたします。みな
さま、ふるってのご参加をお願い
申し上げます。

　なお、会場の関係から人数の調査を行いたいので、ご参加くださる方は、ご所属・氏名
・メールアドレスを、yagihara@mtl.t.u-tokyo.ac.jp（ＪＳＴ事務補佐員　八木原晴水）
までお知らせくださるようお願い申し上げます（申し込みがなければ参加できない、とい
うわけではありません。会場設定のためです）。

●日時：        ２００３年７月３０日（水）
                 Talk-1：　14:00〜15:30
                 Microprocessor Evolution: Past, Present, and Future

                 Talk-2：　16:00〜18:00
                 Speculative Multithreading: from Multiscalar to MSSP

●場所：        東京大学・本郷キャンパス
                 工学部３号館　２F３１号室（人数によって変更の可能性あり）
                 http://www.ee.t.u-tokyo.ac.jp/location-j.html

●問合せ先：
  事務連絡　八木原晴水(JST 事務補佐）
  yagihara@mtl.t.u-tokyo.ac.jp

  内容についてのご質問等　坂井修一（東大・情理工・電情　教授）
                sakai@mtl.t.u-tokyo.ac.jp

●後援・共催
CREST「情報社会を支える新しい高性能情報処理技術」「ディペンダブル情報処理基盤」
ＣＯＥ「情報処理科学技術コア」「大域ディペンダブル情報処理基盤」

●講演概要：

Talk 1: Microprocessor Evolution: Past, Present, and Future

The past decade has seen a tremendous improvement in microprocessor
performance brought on by two factors: faster transistors,
and many more transistors.  A 30-fold increase in the number of
transistors on a microprocessor chip has allowed microprocessor architects
to use a plethora of techniques to improve performance:
multiple instruction issue, out-of-order execution, speculative execution.
Starting with single-issue, in-order execution processors at the beginning of
the past decade, we now routinely have four-issue, out-of-order execution
processors.
This decade promises to be equally exciting for computer architects,
as another 30-fold increase in the transistor budget will enable even more
opportunities.  New opportunities, however, will bring new constraints,
such as wire speeds and power budgets.  Microprocessor architects are
expected to use these new opportunities to continue to improve the
exploitation of instruction-level parallelism (ILP), as well as moving
towards to the exploitation of thread-level parallelism.

This talk will attempt to put the past and (likely) future evolution
of microprocessors into context.  We will discuss the research successes
of the past that have successfully influenced modern microprocessors
(e.g., ILP, out-of-order execution, speculative execution),
current research issues that are likely to impact next-decade microprocessors
(e.g., multithreading, speculative multithreading), as well as
future research issues that are likely to be successful in influencing
future-generation microprocessors.

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Talk 2: Speculative Multithreading: from Multiscalar to MSSP

Single-chip processors currently have microarchitectures capable of supporting
multiple threads of execution (either via multithreading or via chip
multiprocessing),
a capability whose use is likely to continue to increase.  Speculative
multithreading
refers to a broad class of recently proposed techniques to speculatively
``parallelize'' the execution of a sequential program.
My research group at Wisconsin has been working on speculative multithreading
techniques for over a decade.  This talk will overview some of what we have
learned over the years.  We will start with our early work on multiscalar,
continue with data-driven multithreading and speculative slices (a.k.a prefetch
threads or helper threads or scout threads), and then on to our most recent
work on master-slave speculative parallelization.

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