Bringing out “ultralow power” core technology for next-generation systems

Associate Professor Hiroshi Nakamura
(Department of Information Physics and Computing)

Associate Professor Nakamura specializes in computer architecture research and VLSI systems.  His latest interest is low-power LSI, a research that meets contradictory requirements, reducing power consumption while maintaining high-performance.  Since high-performance LSI and low-power technology has immeasurable impact on diverse system development including next-generation supercomputers, servers, personal computers, game consoles, and mobile phones, researchers in electronics around the world are engaged in fierce competition.  Associate Professor Nakamura is breaking ground by introducing new concepts.

Improved performance of VLSI has yielded performance gain in computer systems.  As design rules of transistors that are at the core of VLSI enter the nanometer level, the size starts reaching its limits and leakage power consumed during standby is said to become greater than power consumed by operation.  Associate Professor Nakamura‘s answer to this challenge is “data resident” strategy, which means that “required transistor operations are minimized through data flow optimization and reduced data movement and only the necessary number of transistors run when needed while no electric current is supplied to transistors that need not run.”

Specialists in low-power circuit technology, architecture, and OS researches are engaged to realize this strategy.  High-performance and low-power consumption are common requirements in all IT systems that support the information society.  Associate Professor Nakamura feels the great potential, based on the new idea of optimizing information processing flow in the entire society, that low-power LSI research may offer innovative “high-performance + low-power” system architecture.